1. Field of the Invention
The present invention relates generally to a trapping gate forming process and a flash cell, and more specifically to a trapping gate forming process and a flash cell, which integrates trapping gate forming processes with isolation structure forming processes.
2. Description of the Prior Art
Communication of mass information is a regular part of modern life. Memory devices that access information are essential for managing such information efficiently. Flash memory, with its advantages of low power consumption, high-speed operation, being readable/writable, non-volatile, and requiring no mechanical operations, has been widely applied to personal computers and electronic apparatus, as operations of data writing, reading, and erasing can be performed repeatedly on a non-volatile memory device and the data stored therein will not be lost even when a power supply is turned off.
Flash memory includes a plurality of memory units, wherein each memory unit includes a specially made MOS (Metal-Oxide-Semiconductor) transistor. Each transistor includes a stacked gate having a trapping gate and a control gate fabricated thereon. The control gate is disposed on the trapping gate directly, the trapping gate and the control gate are isolated by a dielectric layer, and the trapping gate and the substrate are isolated by a tunneling oxide (this is known as a stacked gate flash memory). The transistor may have other assisting gates beside the trapping gate and the control gate, and the memory unit may be integrated with transistors of logic units.